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DDR2 SDRAM SO-DIMM
HYMP112S64(L)MP8
Revision History
No. 0.1 History 1) Defined target spec. 2) Corrected Pin assignment table Date July 2004 Remark
128Mx64 bits
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 1
DDR2 SDRAM SO-DIMM
HYMP112S64(L)MP8
DESCRIPTION
128Mx64 bits
Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8 DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64MP8 series provide a high performance 8-byte interface in 67.60mm X 30.00mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMP512S64MP8 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
* * * * * * 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on 128Mx8 DDR2 DDP SDRAMs JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & /CK) Programmable CAS Latency 3 / 4 /5 supported * * Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 7.8us refresh period at Lower than TCASE 85, 3.9us( 85 TCASE 95) * * Serial Presence Detect(SPD) with EEPROM Lead free product
*
ORDERING INFORMATION
Type Part No. HYMP112S64(L)MP8-E4 PC2-3200 (DDR2-400) HYMP112S64(L)MP8-E3 HYMP112S64(L)MP8-C5 PC2-4300 (DDR2-533) HYMP112S64(L)MP8-C4 4-4-4 2 rank 1GB Lead-free SO-DIMM 3-3-3 5-5-5 Description CL-tRCD-tRP 4-4-4 200pin Unbuffered SODIMM 67.60 mm x 30,00 mm (MO-224) Form Factor
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 2
HYMP112S64(L)MP8
PIN Functional Description
Symbol CK[1:0], CK[1:0] Type Polarity Pin Description The system clock inputs. All adress an commands lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and WE define the operation to be excecuted by the SDRAM. Selects which DDR2 SDRAM internal bank of four or eight is activated. Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, difines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data Input/Output pins. Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobe, associated with one data byte, sourced whit data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed approriately. When hign, the PLL outputs are always driven when the PLL input clock is active. When low, the PLL remains locked on the input clock, if active, but output clocks are stopped. Pulled high via 10KY resistor on the SO-DIMM . Only used on DDR2 SO-DIMMs with a PLL. Power supplies for core, I/O, Serial Presense Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. This signals is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. Address pins used to select the Serial Presence Detect base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SODIMMs).
Input
Cross Point
CKE[1:0]
Input
Active High
/S[1:0]
Input
Active Low
/RAS, /CAS, /WE BA[1:0] ODT[1:0]
Input Input Input
Active Low
A[9:0], A10/ AP, A[15:11]
Input
DQ[63:0] DM[7:0]
In/Out Input
DQS[7:0], DQS[7:0]
In/Out
Cross point
RESET
Input
Active Low
VDD, VDDSPD,VSS SDA SCL SA[1:0] TEST
Supply In/Out Input Input In/Out
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HYMP112S64(L)MP8
PIN ASSIGNMENT
Pin NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front Side VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2 Pin NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back Side VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC Pin NO. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front Side DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 Pin NO. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Back Side DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 Pin NO. 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Front Side A1 VDD A10/AP BA0 WE VDD CAS NC/S1 VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin NO. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Back Side A0 VDD BA1 RAS S0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS Pin NO. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front Side DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD Pin NO. 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1
Pin Location
2 40 42 200
Front
1 39 41 199
Back
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HYMP112S64(L)MP8
FUNCTIONAL BLOCK DIAGRAM
3+/- 5% CKE1 ODT1 /S1 CKE0 ODT0 /S0 DQS0 /DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 /DQS1 DM1 DQ8 DQ8 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 /DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 /DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1
DQS4 /DQS4 DM4 DQ32
DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS /DQS DM
/CS0 ODT0 CKE0
/CS1 ODT1 CKE1
D0,D8(DDP)
DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 /DQS5 DM5 DQ40
D4,D12(DDP)
/CS0 ODT0 CKE0
/CS1 ODT1 CKE1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS /DQS DM /CS0 ODT0 CKE0 /CS1 ODT1 CKE1
D1,D9(DDP)
DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 /DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 /DQS7 DM7 DQ56
D5,D13(DDP)
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS0 ODT0 CKE0 /CS1 ODT1 CKE1
D2,D10(DDP)
D6,D14(DDP)
D3,D11(DDP)
DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SCL SCL A0 A1 A2
D7,D15(DDP)
3 +/- 5% BA0-BA2 A0-AN /RAS /CAS /W E SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS D0-15 D0-15 D0-15 D0-15 D0-15
SA0 SA1
Serial PD WP
SDA
SDA
Notes : 1. Unless otherwise noted, resistor values are 22 5% 2. DQ wring may differ form that described in this drawing; however , DQ,DM,DQS,/DQS relationships are maintained as shown.
CK0 4 loads /CK0
V DD SPD V REF
Serial PD SDRAMS DO-D15 SDRAMS DO-D15, V DD and V DD Q SDRAMS DO-D15, SPD
CK1 4 loads /CK1
V DD V SS
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HYMP112S64(L)MP8
ABSOLUTE MAXIMUM RATINGS
Parameter Operating temperature(ambient) DRAM Component Case Temperature Range Operating Humidity(relative) Storage Temperature Storage Humidity(without condensation) Barometric Pressure(operating & storage) Symbol TOPR TCASE HOPR TSTG HSTG PBAR Value 0 ~ +55 0 ~+95 10 to 90 -50 ~ +100 5 to 95 105 to 69
o o
Unit C C 1 2 1 1 1
Note
%
o o
C C
K Pascal
1,3
Note : 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. 3. Up to 9850 ft.
Operating Condtions(AC&DC)
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter Power Supply Voltage Input Reference Voltage EEPROM Supply Voltage Termination Voltage Note : 1. VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device. Symbol VDD VDDQ VREF VDDSPD VTT Min 1.7 1.7 0.49 x VDDQ 1.7 VREF-0.04 Max 1.9 1.9 0.51 x VDDQ 3.6 VREF+0.04 Unit V V V V V 3 1 2 Note
Input DC Logic Level
Parameter Input High Voltage Input Low Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Note
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HYMP112S64(L)MP8
Input AC Logic Level
Parameter AC Input logic High AC Input logic Low Symbol VIH(AC) VIL(AC) Min VREF + 0.250 Max VREF - 0.250 Unit V V Note
AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising edges and the range from VIH(dc) min to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate 1.0 1.0 Value 0.5 * VDDQ V V V/ns Units 1 1 2, 3 Notes
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VSWING(MAX)
delta TF Falling Slew = VIH(dc) min - VIL(ac) max delta TF
delta TR Rising Slew =
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
VIH(ac) min - VIL(dc) max delta TR
< Figure : AC Input Test Signal Waveform >
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HYMP112S64(L)MP8
Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Note: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC). Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Notes 1 2
VDDQ VTR VCP VSSQ
< Differential signal levels >
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
VID
Crossing point
VIX or VOX
Differential AC output parameters
Symbol VOX (ac) Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Notes 1
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HYMP112S64(L)MP8
Output Buffer Levels
Output AC Test Conditions
Symbol VOH VOL VOTR Parameter Minimum Required Output Pull-up under AC Test Load Maximum Required Output Pull-down under AC Test Load Output Timing Measurement Reference Level SSTL_18 Class II VTT + 0.603 VTT - 0.603 0.5 * VDDQ Units V V V 1 Notes
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol IOH(dc) IOL(dc) Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 Class II - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement.
OCD defalut characteristics
Description Output impedance Pull-up and pull-down mismatch Output slew rate Sout Parameter Min 12.6 0 1.5 Nom 18 Max 23.4 4 5 Unit ohms ohms V/ns Notes 1,2 1,2,3 1,4,5,6
Note: 1. Absolute Specifications (0C TCASE +95C; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from vil(ac) to vih(ac). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. 6. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins. Output slew rate at 667&800MT/s will be added with JEDEC process.
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HYMP112S64(L)MP8
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz )
Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Note : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. CK0, /CK0 CKE0, /CS Address, /RAS, /CAS, /WE DQ,DM,DQS, /DQS Pin Symbol CCK CI1 CI2 CIO Min, 15 44 27 8 Max, 33 65 65 12 Unit pF pF pF pF
IDD Specifications
HYMP112S64(L)MP8 Parameter Operating one bank active-precharge current Operating one bank active-read-precharge current Precharge power-down current Precharge quiet standby current Precharge standby current Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) Active power-down current IDD3P(S) Active Standby Current Operating burst read current Operating Current Burst auto refresh current IDD3N IDD4R IDD4W IDD5B IDD6 Self Refresh Current IDD6(L) Operating bank interleave read current IDD7 48 1960 48 2160 mA mA 48 720 1320 1320 1560 80 64 840 1440 1440 1600 80 mA mA mA mA mA mA PC2 3200 max. 920 1000 48 520 560 240 PC2 4300 Unit max. 1040 1120 64 600 640 320 mA mA mA mA mA mA Note
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HYMP112S64(L)MP8
IDD Meauarement Conditions
Symbol IDD0 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 Units mA
IDD1
mA
IDD2P IDD2Q IDD2N
mA mA mA mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD7
mA
Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.1/ July 2004 11
HYMP112S64(L)MP8
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS DDR2-533(C4) 4-4-4 min 4 15 15 60 45 DDR2-533(C5) 5-5-5 min 5 18.75 18.75 63.75 45 DDR2-400(C3) 3-3-3 min 3 15 15 55 40 DDR2-400(C4) 4-4-4 min 4 20 20 65 45 ns ns ns ns ns Unit
AC Timing Parameters by Speed Grade
Parameter Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew Clock High Level Width Clock Low Level Width Clock Half Period System Clock Cycle Time DQ and DM input hold time DQ and DM input setup time Control & Address input Pulse Width for each input DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Rev. 0.1/ July 2004 Symbol tAC tDQSCK tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD DDR2-400 Min -600 -500 0.45 0.45 min (tCL,tCH) 5000 400 400 0.6 0.35 tAC min 2*tAC min tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 Max 600 500 0.55 0.55 8000 tAC max tAC max tAC max 350 450 WL + 0.25 DDR2-533 Min -500 -500 0.45 0.45 min (tCL,tCH) 3750 350 350 0.6 0.35 tAC min 2*tAC min tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 Max 500 450 0.55 0.55 8000 tAC max tAC max tAC max 300 400 WL + 0.25 Unit ps ns CK CK ns ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK 12 1 1 Note
HYMP112S64(L)MP8
- continued DDR2 400 Min 0.4 0.25 600 600 0.9 0.4 105 7.5 2 15 (tWR/tCK) + (tRP/tCK) 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 7.8 3.9 12 2 tAC(max)+1 2tCK+ tAC(max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1 Max 0.6 1.1 0.6 DDR2 533 Min 0.4 0.25 500 500 0.9 0.4 105 7.5 2 15 (tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 7.8 3.9 12 2 tAC(max)+1 2tCK+ tAC(max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1 Max 0.6 1.1 0.6 -
Parameter Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay CAS to CAS command delay Write recovery time Auto Precharge Write Recovery + Precharge Time Write to Read Command Delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any nonread command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval
Symbol tWPST tWPRE tIH tIS tRPRE tRPST tRFC tRRD tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
t t
Unit tCK tCK ps ps tCK tCK ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us
Note
CKE
AOND
t
AON
t
AONPD
t
AOFD
t
AOF
t
AOFPD tAXPD tOIT tDelay tREFI tREFI
tANPD
2 3
Note : 1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G821(L)M). 2. 0C TCASE 85C 3. 85C TCASE 95C Rev. 0.1/ July 2004 13
HYMP112S64(L)MP8
PACKAGE OUTLINE
Front
67.60 20.00 Min
Side
3.8 max
4.00 +/-0.10
30.00 20.00
PIN 1 PIN 39 PIN 41 PIN 199
11.40 2.70 4.20 2.45 11.40 2.40
PIN 2
1.00 +/- 0.10 6.00
Back
4.20
PIN 40 PIN 42
47.40
PIN 200
note: 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 0.1/ July 2004
14
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(128Mx64 Unbuffered Lead-free DDR2 SO-DIMM)
Rev. 0.1/ July 2004
15
HYMP112S64(L)MP8
SERIAL PRESENCE DETECT
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Function Description Number of bytes utilized by module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of DIMM ranks Module data width Module data width (continued) Voltage Interface level of this assembly DDR SDRAM cycle time at CL=5 DDR SDRAM access time from clock (tAC) DIMM Configuration type Refresh Rate and Type Primary DDR SDRAM width Error Checking DDR SDRAM data width Reserved Burst Lengths Supported Number of banks on each SDRAM Device CAS latency supported Reserved DIMM Type DDR SDRAM module attributes DDR SDRAM device attributes : General DDR SDRAM cycle time at CL=4(tCK) DDR SDRAM access time from clock at CL=4(tAC) DDR SDRAM cycle time at CL=3(tCK) DDR SDRAM access time from clock at CL=3(tAC) Minimum Row Precharge Time(tRP) Minimum Row Activate to Row Active delay(tRRD) Minimum RAS to CAS delay(tRCD) Minimum active to precharge time(tRAS) Module rank density Address and command input setup time before clock (tIS) Address and command input hold time after clock (tIH) Data input setup time before clock (tDS) Data input hold time after clock (tDH) Write recovery time(tWR) Internal write to read command delay(tWTR) Internal read to precharge command delay(tRTP) Memory analysis probe characteristics Extension of byte 41 tRC and byte 42 tRFC Minimum active / auto-refresh time ( tRC) Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4), C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5) Speed Grade all all all all all all all all all E3,E4 C4,C5 E3,E4 C4,C5 all all all all all all all all all all E3,E4,C5 C4 E3,E4,C5 C4 E3,C4 E4,C5 E3,C4 E4,C5 E3, C4 E4 C5 all E3, C4 E4 C5 E3 E4,C4,C5 all E3, E4 C4, C5 E3, E4 C4, C5 E3, E4 C4, C5 E3, E4 C4, C5 all E3, E4 C4, C5 all E3,E4,C4 C5 E3 C4 E4 C5 Function Supported 128 Bytes 256 Bytes DDR2 SDRAM 14 10 30.0mm/stack/2rank 64 Bits SSTL 1.8V 5.0 ns 3.75 ns +/-0.6ns +/-0.5ns non-ECC 7.8us & Self refresh x8 None 4,8 4 3, 4, 5 SO-DIMM Normal 5.0ns 3.75ns +/-0.6ns +/-0.5ns 5.0ns Undefined +/-0.6ns Undefined 15ns 20ns 18.75ns 7.5ns 15ns 20ns 18.75ns 40ns 45ns 512MB 0.6ns 0.5ns 0.6ns 0.5ns 0.40ns 0.35ns 0.40ns 0.35ns 15ns 10ns 7.5ns 7.5ns Undefined Undefined tRC extended 55ns 60ns 65ns 63.75ns Hexa Value 80 08 08 0E 0A 71 40 00 05 50 3D 60 50 00 82 08 00 00 0C 04 38 00 04 00 00 50 3D 60 50 50 00 60 00 3C 50 4B 1E 3C 50 4B 28 2D 80 60 50 60 50 40 35 40 35 3C 28 1E 1E 00 00 50 37 3C 41 3F Note
1 1
2 2
2 2 2 2
Rev. 0.1/ July 2004
16
HYMP112S64(L)MP8
- continued Byte# 42 43 44 45 46 47~61 62 63 64 65~71 Function Description Minimum auto-refresh to active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) Maximim DQS-DQ skew time(tDQSQ) Maximum read data hold skew factor(tQHS) PLL Relock time Superset information(may be used in future) SPD Revision code Checksum for Bytes 0~62 Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code Speed Grade all all E3, E4 C4, C5 E3, E4 C4, C5 Function Supported 105ns Hexa Note Value 69 80 23 1E 2D 28 00 00 10 C5 4C 3F 23 AD 00 0* 1* 2* 3* 4* 5* 48 59 4D 50 31 31 32 53 36 34 4D 50 38 2D 45 43 33 34 35 20
72
Manufacturing location
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89~90 91 92 93 94 95~98 99~127 128~255
Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR2 SDRAM) ---------Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Package type) Manufacture part number(Package material) Manufacture part number(Component configuration) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) -------Manufacture part number(Minimum cycle time) Manufacture part number(T.B.D) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may be used in future) Open for customer use
8.0ns 0.35ns 0.30ns 0.45ns 0.40ns No PLL Undefined 1.0 E3 E4 C4 C5 Hynix JEDEC ID Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area H Y M P 1 1 2 S 6 4 M P 8 `-' E3, E4 E C4, C5 C E3 3 E4,C4 4 C5 5 Blank
6
Undefined Undefined
00 00
3 3 4 5 5
Note : 1. The bank address is excluded 2. This value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix's own Module Serial Number System 5. These bytes undefined and coded as `00h' 6. Refer to Hynix Web Site
Byte 83~84, Low Power Part
Byte # 83 84 Function Description Manufacture part number(Low power part) Manufacture part number(Package type) Speed Grade Function Supported L M Hexa Value 4C 4D Note
Rev. 0.1/ July 2004
17

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